add riscv64 support

2026-02-05 11:08:54 +08:00 · 2025-05-02 10:27:10 -04:00 · 2025-05-02 10:27:10 -04:00 · efeece61de
commit efeece61de
parent 3d51e391c7
1 changed files with 2 additions and 0 deletions
--- a/ci/ci.py
+++ b/ci/ci.py
@ -396,6 +396,8 @@ class CI(SetEnvs):
                return "arm64"
            case "arm32":
                return "arm"
+            case "riscv":
+                return "riscv64"
            case _:
                return "amd64"