From efeece61de5397fbdc19bced5eee6f26165a89c6 Mon Sep 17 00:00:00 2001
From: aptalca <541623+aptalca@users.noreply.github.com>
Date: Fri, 2 May 2025 10:27:10 -0400
Subject: [PATCH] add riscv64 support

---
 ci/ci.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/ci/ci.py b/ci/ci.py
index d3cfb66..b74d291 100755
--- a/ci/ci.py
+++ b/ci/ci.py
@@ -396,6 +396,8 @@ class CI(SetEnvs):
                 return "arm64"
             case "arm32":
                 return "arm"
+            case "riscv":
+                return "riscv64"
             case _:
                 return "amd64"